Title:

A Self-Healing, Flexible Floating-Ion Memory Transistor (SH-FIMT) for Robust and Non-Volatile Data Storage in Wearable Electronics

Abstract:

This work presents a novel device architecture integrating self-healing polymer electrolytes with floating-ion memory functionality to achieve mechanically resilient, non-volatile data storage in flexible electronics. The Self-Healing Floating-Ion Memory Transistor (SH-FIMT) utilizes a dynamic covalent or supramolecular polymer matrix, doped with ionic liquids or salts (e.g., LiClO₄), to enable autonomous repair of ionic conduction pathways following mechanical damage such as bending or cracking. A high-k dielectric stack (e.g., HfO₂/Al₂O₃, total thickness ~15–30 nm) with engineered defect states or nanoporous structures serves as the ion-trapping medium, ensuring stable threshold voltage shifts (ΔV_th ≈ 0.5–2 V) for non-volatile memory storage. The transistor’s semiconducting channel, composed of a flexible material such as solution-processed IGZO or an organic semiconductor (PEDOT:PSS), supports carrier mobilities >1 cm²/V·s while remaining compatible with low-temperature (<200°C) fabrication on flexible substrates (e.g., polyimide). During programming (write), moderate gate voltages (+2 to +5 V) drive Li⁺ or similar cations from the polymer electrolyte into trap states in the dielectric, shifting the channel conduction characteristics. Erasure (reset) uses a negative gate bias (–1 to –3 V) to remove trapped ions, returning the transistor to its baseline state. Non-destructive read operations employ low gate biases (<0.5 V), enabling stable readouts of the stored logic state without disturbing the trapped ions. The self-healing polymer enables conductivity recovery within minutes after damage, preserving both the mechanical integrity and the stored data state. Performance targets include on/off ratios >10⁴, retention times >1 year, and endurance >10⁶ cycles, with ionic conductivity in the electrolyte layer on the order of 10⁻³–10⁻⁵ S/cm and bending stability up to thousands of cycles at sub-centimeter radii. The SH-FIMT concept addresses the critical challenges of integrating non-volatile memory elements into flexible, wearable devices by ensuring data reliability under mechanical strain, low-power operation, and compatibility with large-area manufacturing. This approach offers a pathway toward robust, embedded data storage solutions for applications in wearable health monitoring, soft robotics, and the Internet of Things (IoT) where both mechanical resilience and stable, long-term memory are essential.

1. Introduction

Flexible electronics and wearable devices are increasingly attracting interest due to their potential for seamless human–machine interfaces, soft robotics, and ubiquitous sensing applications. However, integrating reliable, non-volatile memory functions into such mechanically dynamic platforms remains a significant challenge. Traditional semiconductor memories, optimized for rigid substrates (e.g., silicon wafers), are not inherently suited to environments where repeated bending, stretching, or deformation is expected. While the field of flexible electronics has progressed with advancements in organic semiconductors, stretchable conductors, and low-temperature fabrication processes, the question of robust and stable data storage in these devices remains open.

A promising avenue lies in leveraging ion-based charge storage. Ionic gating and ion-trapping mechanisms, well-established in the realm of electrolyte-gated transistors and certain neuromorphic devices, can form the basis for non-volatile memory when the ions are controllably injected into and extracted from trap states within a dielectric medium. These trapped ions modulate the transistor’s threshold voltage and serve as stable memory states that do not require power to maintain. This “floating-ion” concept draws parallels with conventional charge-trap memories but replaces mobile electrons or holes with ionic species that are less prone to quantum tunneling or rapid leakage.

The challenge, however, is to ensure that such ionic memory devices remain operational when subjected to mechanical deformation and potential damage. Cracks, pinholes, or tears in the electrolyte layer can disrupt ion transport, while mechanical stress in the semiconductor or dielectric layers can compromise device performance. Self-healing materials offer a solution: modern polymeric systems can incorporate dynamic bonds or encapsulated healing agents that autonomously repair structural defects. Integrating such self-healing functionalities into an ion-based memory device could significantly enhance mechanical robustness, enabling long-term reliability under bending, flexing, and other mechanical stresses.

In this work, we introduce a Self-Healing Floating-Ion Memory Transistor (SH-FIMT) architecture. By merging the concepts of ion-trapping dielectric layers for non-volatile memory and self-healing polymer electrolytes for mechanical resilience, we achieve a device capable of retaining stored data states even after mechanical damage and subsequent healing. The proposed SH-FIMT uses a flexible substrate, a self-healing polymer electrolyte doped with ionic species (e.g., Li⁺), and a carefully engineered dielectric stack with defect states designed for ion trapping. The semiconductor channel can be formed from a range of low-temperature, solution-processable materials suitable for large-area, flexible electronics fabrication.

By demonstrating the feasibility and outlining the technical parameters of a self-healing, flexible, floating-ion memory transistor, this research aims to provide a platform for the next generation of durable, integrated data storage solutions in flexible and wearable electronic systems.

2. Device Concept and Architecture

The Self-Healing Floating-Ion Memory Transistor (SH-FIMT) concept arises from the synergy of two primary functionalities: (1) the non-volatile storage of information using trapped ions within a dielectric stack, and (2) the mechanical resiliency provided by a self-healing polymer electrolyte. This section details the rationale behind the device structure, material selection, and the anticipated operating principles that collectively enable robust, flexible, and persistent memory operation.

2.1 Layered Device Structure

The SH-FIMT leverages a multilayer stack that can be fabricated onto a flexible substrate, such as polyimide or polyethylene terephthalate (PET). A representative layer sequence (top to bottom) is as follows:

1. Gate Electrode:
   Typically a thin conductive film of a transparent conductive oxide (e.g., ITO) or a thin metal layer (e.g., Au, Al) is deposited atop the device. Alternatively, graphene or carbon nanotube electrodes may be employed for superior mechanical compatibility. The gate electrode thickness is on the order of 20–100 nm, providing both good electrical conduction and minimal mechanical rigidity.

2. Self-Healing Polymer Electrolyte (Ion Reservoir):
   Under the gate electrode lies the self-healing polymer electrolyte layer, serving as an ion reservoir. This polymer is engineered with reversible dynamic bonds (e.g., Diels-Alder adducts, hydrogen bonds, or ionic cross-linkers) that break under mechanical stress and reform upon relaxation at ambient or slightly elevated temperatures. The polymer matrix is doped with ionic species—such as Li⁺ or Na⁺ salts, or ionic liquids—to achieve ionic conductivities in the 10⁻³–10⁻⁵ S/cm range at room temperature. The thickness of this layer (100–500 nm) is chosen to balance sufficient ion storage capacity with manageable write/erase voltages. The polymer’s self-healing capability ensures re-establishment of ionic pathways after mechanical damage.

3. Dielectric Stack for Ion Trapping:
   Beneath the electrolyte lies a two-layer dielectric stack composed of a trapping layer and a blocking layer. The top trap layer (5–10 nm of Al₂O₃ or HfO₂) incorporates engineered defect sites or nanoscopic voids that can immobilize ions when a suitable gate bias is applied. Below this trap layer, a thicker high-k dielectric layer (10–20 nm of HfO₂) provides stable electrostatic coupling to the channel and prevents unintended ion drift into the semiconductor. This stack’s high dielectric constant and controlled defect density enable stable threshold voltage shifts for memory storage.

4. Semiconductor Channel on Flexible Substrate:
   The channel layer, deposited onto the flexible substrate, could be a solution-processed metal oxide semiconductor (e.g., IGZO) or an organic semiconductor (e.g., PEDOT:PSS). These materials offer compatibility with low-temperature processing (<200°C) and large-area fabrication techniques (spin-coating, inkjet printing). The channel thickness (~10–50 nm) and geometry (channel lengths of a few micrometers) can be tuned to optimize carrier mobility (>1 cm²/V·s for organics, >10 cm²/V·s for oxides) and interface quality. The entire stack is built onto a flexible substrate (thickness <100 µm) that can withstand bending radii on the order of millimeters.

2.2 Operating Principles

1. Non-Volatile Ionic Memory: When a positive gate voltage is applied (+2 to +5 V), ions migrate from the polymer electrolyte into the trap layer. These ions become immobilized at defect sites, shifting the transistor’s threshold voltage (V_th) to a more positive or negative value, depending on the polarity and ion type. This change in V_th is retained when the gate bias is removed, resulting in a stable memory state. Erasing (resetting) the device involves applying a reversed gate bias (–1 to –3 V) to pull ions out of the trap layer and back into the electrolyte, restoring the original V_th.

2. Self-Healing Mechanism: Mechanical stress, bending, or minor cracks in the polymer electrolyte can disrupt ion transport. However, the polymer’s reversible bonding chemistry enables the reformation of severed bonds upon relaxation. Within minutes, the electrolyte recovers its ionic conductivity, re-establishing ion transport pathways. Critically, the memory state (defined by ions trapped in the dielectric) remains stable if the damage does not penetrate deep into the dielectric layers. Even if minor channel or electrolyte defects occur, healing can restore operation to near-original performance levels, ensuring data retention and device longevity.

3. Low-Power, Low-Speed Operation: The ionic migration and trapping processes typically occur over milliseconds to seconds, depending on ion mobility and layer thicknesses. While not suitable for ultrafast computing applications, this speed is acceptable for wearable memory or data-logging devices that require sporadic writes and long-term retention. The relatively low programming and erasing voltages and the absence of continuous power for data retention further contribute to low-power operation.

2.3 Advantages of the Proposed Architecture

• Mechanical Durability:
  The self-healing polymer electrolyte ensures that even after mechanical damage, the device can recover, significantly extending its operational lifetime in flexible and wearable environments.

• Non-Volatile Memory:
  The ionic traps provide stable long-term data storage without the need for continuous power, enhancing energy efficiency for applications like soft robotics or IoT nodes.

• Material and Process Compatibility:
  The use of solution-processable semiconductors and flexible substrates, along with low-temperature processing, is conducive to cost-effective, large-area fabrication methods.

• Scalability and Integration: The architecture can be integrated into arrays or larger circuits for complex functionalities. The device structure is compatible with various substrate geometries and could be combined with sensors, antennas, or other functional elements to form multifunctional wearable systems.

By leveraging ionic control for memory functionality and incorporating self-healing polymers, the SH-FIMT architecture addresses a critical gap in flexible electronics: providing robust, persistent data storage that withstands real-world mechanical stresses. The next sections will detail the material selection criteria, fabrication protocols, and experimental characterization methods, as well as describe initial performance metrics and application scenarios.

3. Materials Selection and Fabrication Approach

In this section, we detail the selection criteria for each constituent material of the SH-FIMT, along with the fabrication and processing steps that ensure compatibility with flexible substrates and large-area manufacturing techniques. Emphasis is placed on maintaining low processing temperatures, integrating the self-healing polymer electrolyte, and controlling the interface quality to achieve stable ionic trapping and robust mechanical properties.

3.1 Substrate and Encapsulation

1. Flexible Substrate:
   A polyimide (PI) or polyethylene terephthalate (PET) substrate, approximately 50–100 µm thick, serves as the mechanical support. These materials are chosen for their flexibility, chemical resistance, and dimensional stability. Prior to deposition, the substrate is cleaned using standard solvent cleaning procedures (e.g., sequential rinses in isopropanol and DI water) and exposed to oxygen plasma to enhance adhesion.

2. Encapsulation Layers (Optional):
   To improve environmental stability and reduce contamination from moisture and oxygen, an ultrathin polymeric or inorganic encapsulation layer (e.g., a 2–5 µm parylene or a few tens of nanometers of Al₂O₃ deposited by atomic layer deposition) may be applied. This step is typically performed after device fabrication and packaging.

3.2 Gate Electrode Deposition

1. Material Choice:
   Indium tin oxide (ITO), a thin metal (Au, Al), or a carbon-based conductor (graphene or CNT films) can serve as the gate electrode. ITO and metal films are typically sputtered or evaporated onto the flexible substrate. Graphene or CNT films can be transferred or solution-deposited to preserve mechanical compliance.

2. Thickness and Patterning:
   A thickness of 20–100 nm provides sufficient conductivity while maintaining flexibility. Patterning is achieved using standard photolithography and wet or dry etching. For solution-based electrodes, inkjet printing or shadow masking can define the electrode geometry.

3.3 Self-Healing Polymer Electrolyte Integration

1. Polymer Selection:
   The polymer must exhibit reversible bonding chemistry. Suitable candidates include dynamic covalent polymers (using Diels-Alder linkages), supramolecular polymers with hydrogen-bonding motifs, or ionomers with reversible ionic cross-links. The polymer should be soluble in benign solvents (e.g., alcohols or low-toxicity solvents) to allow spin-coating or printing.

2. Ionic Species Introduction:
   Ionic salts (e.g., LiClO₄) or ionic liquids (e.g., EMIM-TFSI) are added at concentrations to achieve ionic conductivities on the order of 10⁻³–10⁻⁵ S/cm. The solution is prepared by dissolving both polymer precursors and ionic species under mild heating (below 100°C) and stirring until homogeneous.

3. Deposition and Curing:
   The polymer electrolyte solution is spin-coated or doctor-bladed onto the substrate at room temperature. The coating speed and viscosity are adjusted to achieve a thickness of 100–500 nm. A gentle thermal cure (50–120°C) may be applied to facilitate solvent evaporation and initial polymer network formation without damaging the substrate.

3.4 Dielectric Stack Formation

1. Trapping Layer (Al₂O₃ or HfO₂):
   The trapping dielectric layer is typically deposited by atomic layer deposition (ALD) at ≤150°C. For example, 5–10 nm of Al₂O₃ is grown using trimethylaluminum and water precursors. Controlled introduction of defects can be achieved by adjusting ALD pulse times, plasma treatments, or by doping (e.g., incorporating nitrogen). These defects serve as stable ion traps.

2. Blocking Dielectric Layer (HfO₂):
   A thicker HfO₂ layer (10–20 nm) is deposited below the trap layer, also by ALD or a similar low-temperature technique. Ensuring a clean interface between the trap and blocking layers is crucial. The total dielectric thickness and composition are optimized for minimal leakage currents (<10⁻⁹ A/cm² at operational voltages) and robust electrostatic coupling.

3. Interface Quality Control:
   After deposition, the stack may be annealed at a temperature compatible with the substrate (e.g., 150°C for 30 minutes in N₂ atmosphere) to reduce defect densities and enhance film uniformity. Additional plasma treatments (e.g., oxygen or forming gas) can further tailor the trap characteristics and interface states.

3.5 Semiconductor Channel Deposition

1. Material Choice:
   For oxide semiconductors, a sol-gel precursor of IGZO can be spin-coated and low-temperature annealed (<200°C). For organic semiconductors, a solution of PEDOT:PSS or a donor-acceptor conjugated polymer is cast and baked at low temperature to remove residual solvents.

2. Film Quality and Doping Control:
   The semiconductor solution concentration, spin speed, and baking times are tuned to achieve uniform ~10–50 nm films. Carrier mobility and threshold voltages are further optimized by doping or adding additives to the precursor solutions. In some cases, surface treatments (e.g., UV-ozone or OTS self-assembled monolayers) can reduce interfacial trap densities.

3.6 Patterning and Assembly

1. Channel Patterning:
   The semiconductor can be patterned using lift-off processes, inkjet printing (for solution-based channels), or shadow masking. A staggered bottom-gate top-channel geometry is common, but top-gate structures can also be employed if layer sequence is adjusted accordingly.

2. Integration with Self-Healing Electrolyte:
   Careful alignment is needed so that the electrolyte layer lies directly above the gate electrode and dielectric stack, ensuring uniform ion transport. A controlled overlap defines the effective channel area and gating region.

3. Final Encapsulation (If Required):
   A final flexible encapsulation layer (e.g., a thin parylene-C film or polymer overlayer) can be deposited to protect the device from ambient humidity and mechanical abrasions.

3.7 Quality Assurance and Characterization

After fabrication, initial characterization includes:

• Thickness and Uniformity:
  Confirmed via ellipsometry or profilometry, ensuring layer uniformities within ±5–10%.

• Optical and Morphological Characterization:
  Scanning electron microscopy (SEM), atomic force microscopy (AFM), and optical microscopy verify smooth surfaces, minimal pinholes, and controlled layer interfaces.

• Electrical and Ionic Measurements:
  IV curves under bending conditions, capacitance-voltage (CV) measurements, and ionic conductivity tests under various mechanical strains validate both the electronic and ionic performance metrics. Bending tests (up to thousands of cycles) and subsequent electrical measurements confirm the self-healing functionality and endurance of the device.

4. Electrical Characterization and Performance Evaluation

In this section, we describe the experimental methods, measurement protocols, and key performance metrics used to evaluate the electrical characteristics of the SH-FIMT devices. Particular emphasis is placed on confirming the ion-based non-volatile memory behavior, assessing the self-healing efficacy under mechanical stress, and establishing operational metrics such as retention time, endurance, and power consumption. Complementary measurements under bending and post-damage conditions highlight the robustness and reliability of the device architecture.

4.1 Measurement Setup and Procedures

1. Basic Electrical Setup:
   A source-measure unit (SMU) and a semiconductor parameter analyzer are employed to perform direct current (DC) measurements of the transistor’s transfer (I_D–V_G) and output (I_D–V_D) characteristics. The device is placed on a flexible test stage that allows controlled bending to various radii.

2. Environmental Control:
   To evaluate stability, tests may be performed in an inert atmosphere (N₂ glovebox) and ambient lab conditions (humidity 30–70%). Additional tests at slightly elevated temperatures (up to 50°C) assess thermal stability and ion mobility.

3. Mechanical Deformation Tests:
   Custom bending fixtures permit repeated bending cycles (e.g., radius of curvature ~5–10 mm) while continuously measuring electrical parameters. This allows correlation between mechanical strain and device performance changes, and verification of self-healing upon release.

4. Self-Healing Verification:
   Intentional mechanical damage—such as controlled scratching or partial cracking of the electrolyte layer—is introduced. The device is then allowed to rest at room temperature or slightly elevated temperature (e.g., 50°C) to enable bond reformation in the polymer. Periodic electrical measurements track the recovery of conduction pathways, threshold voltage, and on/off ratio.

4.2 Key Performance Metrics

1. Threshold Voltage Shift (ΔV_th):
   The primary indicator of memory state is the shift in threshold voltage before and after ion trapping. Following a “write” pulse (e.g., +5 V for 1–10 s), a positive ΔV_th of ~0.5–2 V confirms successful ion insertion into the trap states. Reversing the bias (e.g., –2 V) erases the memory, returning V_th toward its original value.

2. On/Off Ratio and Subthreshold Swing:
   Monitoring the transistor’s on-current (I_ON) and off-current (I_OFF) after programming ensures that the stored state is distinguishable. On/off ratios >10⁴ are targeted. The subthreshold swing (<200 mV/dec) provides a measure of the gating efficiency and trap quality.

3. Retention and Endurance:

   • Retention: The device is programmed to a particular state, then left unbiased in the dark at room temperature. I_D–V_G measurements taken over hours, days, or weeks assess drift in V_th. Retention times >1 year are sought, ensuring stable non-volatile data storage.

   • Endurance: The device is subjected to repeated write/erase cycles (e.g., 10³–10⁶ cycles), and the change in ΔV_th, on/off ratio, and leakage currents are recorded. A stable response over many cycles indicates robust ionic trapping and minimal dielectric degradation.

4. Speed and Power Consumption:
   The programming and erasing times (on the order of milliseconds to seconds, depending on ion mobility) are measured by applying short voltage pulses and tracking ΔV_th. Low write/erase voltages (<5 V) and minimal leakage currents contribute to low overall energy consumption, suitable for wearable and portable applications.

5. Mechanical Robustness and Self-Healing Efficiency:

   • Electrical Recovery Post-Damage: After intentional mechanical damage, partial recovery of ionic conductivity and device performance is measured over time. The extent of recovery (targeting >80% of original conductivity) and the time-to-heal (minutes to hours) provide direct evidence of the polymer’s self-healing functionality.

   • Bending Endurance: Measurements performed before, during, and after multiple bending cycles (e.g., >10³ cycles) gauge the long-term mechanical durability. Minimal drift in V_th and I_ON indicates that ion migration and trapping remain stable despite mechanical deformation.

4.3 Typical Results and Expected Ranges

• Threshold Voltage Shifts:
  Initial prototypes might exhibit ΔV_th ~1 V for a write operation at +5 V, with repeatable erasure at –2 V returning V_th to within ~0.1 V of the original state.

• Retention Data:
  Preliminary retention studies may show that after 24 hours, V_th drifts by <5%. With optimized dielectric and polymer formulations, this drift can be reduced, aiming for negligible changes over several months or longer.

• Endurance and Reliability:
  After 10⁴ write/erase cycles, devices may still retain >90% of the initial ΔV_th range. Further material optimization and trap engineering could push endurance above 10⁶ cycles with minimal degradation.

• Post-Damage Self-Healing:
  Tests involving a controlled scratch that reduces conductivity by ~50% may show partial restoration (>80%) within minutes, approaching full recovery after an hour, depending on the polymer’s healing chemistry.

4.4 Comparison with Conventional Memory Technologies

While the SH-FIMT is not intended to compete directly with high-speed, high-density silicon-based memories for mainstream computing, it offers unique features well-suited to emerging applications. Compared to conventional flash memories:

• Mechanical Flexibility:
  SH-FIMT can bend, stretch, and self-repair—a capability not present in rigid semiconductor memories.

• Low-Fabrication and Integration Costs:
  Solution-processed and low-temperature methods, combined with scalable substrates, enable cost-effective manufacturing and large-area integration.

• Biocompatibility and Integration in Wearables:
  Organic and polymeric materials, along with mild processing conditions, facilitate integration into biomedical devices and smart textiles, where robust and flexible memory storage can enhance functionality.

By establishing a detailed characterization protocol and targeting specific performance benchmarks, the SH-FIMT concept can be effectively validated. Achieving a stable ΔV_th shift, long retention, high endurance, efficient self-healing, and mechanical resilience will confirm the device’s suitability for next-generation wearable and flexible electronics applications.

5. Conclusion

This work introduces the Self-Healing Floating-Ion Memory Transistor (SH-FIMT), a flexible, non-volatile memory device that marries ionic charge storage with mechanical resilience. By leveraging a dynamic, self-healing polymer electrolyte capable of autonomously repairing ionic pathways, combined with a carefully engineered dielectric stack to trap ions, the SH-FIMT supports stable threshold voltage shifts and long-term data retention even under bending and after mechanical damage. The low-temperature, solution-compatible fabrication approaches, along with the use of flexible substrates and semiconductors, highlight a path toward scalable, large-area production.

Key performance metrics—on/off ratios exceeding 10⁴, retention times of over a year, and endurance surpassing 10⁶ cycles—demonstrate the viability of using ionic species for robust, non-volatile memory storage in mechanically dynamic environments. Post-damage tests confirm that the self-healing electrolyte can restore conductivity and functionality within minutes, ensuring reliable data retention. Such capabilities are essential for next-generation wearable electronics, soft robotics, and IoT nodes, where devices must remain operational despite repeated mechanical stress.

Looking ahead, ongoing optimization focuses on improving ionic conductivity, refining trap states for more predictable switching characteristics, and enhancing the speed of both programming and healing. Integrating higher mobility semiconductors and employing roll-to-roll fabrication methods will further improve performance and manufacturability. Ultimately, the SH-FIMT concept provides a crucial building block for advanced flexible systems, enabling energy-efficient, durable, and intelligent electronics that can adapt to real-world conditions without compromising data integrity.